CMOS dynamic circuits are widely used in VLSI design when high speed operation is required. However, CMOS dynamic circuits suffer from problems relating to race, clock skew and slew rate, charge redistribution, and DC power consumption. One type of CMOS logic, referred to herein as "Domino", is disclosed in R. H. Karambeck, C. M. Lee, H-S. Law, "High-speed Compact Circuits with CMOS," IEEE I. Solid-State Circuits, Vol. 17, pp. 614-619, June 1982. The Domino CMOS logic suffers from a significant disadvantage in that it is non-inverting.
Another prior art CMOS logic is disclosed in N. F. Goncalves and H. J. De Man, "NORA: A Race-free Dynamic CMOS Technology for Pipelined Logic Structures" IEEE J. Solid-State Circuits, Vol-18, pp.261-266, June 1983. Both NORA and Domino CMOS logic suffer from charge redistribution problems.
Further prior art CMOS logic designs are described in J. Yuan and C. Svensson, "High-speed CMOS Circuit Technique", IEEE J. Solid-State Circuits, Vol-24, pp. 62-70, February 1989 and C. M. Lee, and E. W. Szeto, "Zipper CMOS", IEEE Circuits Devices Mag., pp 10-16, May 1986. Each of the NORA, single phase design of Yaun et al and the Zipper CMOS methodology require the use of low-speed P-Logic blocks. Furthermore, the Zipper CMOS consumes DC power and requires a proprietary Zipper driver.
Yet another prior art CMOS logic is disclosed in C. Y. Wu. K. H. Cheng and J. S. Wang, "Analysis and Design of a New Race-free Four-phase CMOS Logic", IEEE J. Solid-State Circuits, Vol. 28, pp. 18-25, January 1993. This four-phase dynamic logic also consumes DC power and requires a complicated clock distribution system.